Clock divider circuits are useful in a number of applications, particularly in counters, where a complete cycle of an output signal represents a predetermined number of incoming clock cycles. The cycles of the output signal can be used to "count" the incoming clock cycles.
It is desirable for such clock divider circuits to work at low power and at high frequencies. For example, desired operating parameters might be a current consumption of 10 .mu.A at a supply voltage of 3.3 V, with an operating frequency of around 100 MHz. It is also desirable that such divider circuits consume a minimum amount of silicon when implemented on an integrated circuit.
Existing counters are generally based on binary counters. Such counters are optimally designed to divide by 2". However, for other even numbers some concatenation of dividing circuits is frequently required to provide the required dividing factor. This increases signal path length and introduces unwanted delays.